18. Cache Test Mode

18.3 Entering Cache Test Mode

Rather than negating SysReset* at the end of the reset sequence, the external agent loads the mode bits into the processor by driving the mode bits (with the CTM signal asserted) on SysAD(63:0), waits at least two SysClk cycles, and then asserts SysGnt* for at least one SysClk cycle.

After waiting at least another 100 ms, the external agent may issue the first cache test mode command.

Figure 18-1 shows the cache test mode entry sequence.

Figure 18-1 Cache Test Mode Entry Sequence